Description: 简易数字频率计利用复杂可编程逻辑器件FPGA,VHDL编程将所有功能模块集成在一块芯片上。功能模块包括时基脉冲发生器、计数器、数据锁存器和显示电路4部分。设计时先分别设计各功能模块，并调试得到正确仿真结果，然后将各个功能模块组合起来。最后作整体仿真、下载，得到实物。由于采用纯数字硬件设计制作，稳定性、可靠性远远高于使用单片机或模拟方式实现的系统，外围电路简单。该数字频率计达到预期要求，实现了可变量程测量，测量范围0.1Hz—9999MHz，精度可达0.1Hz。-Simple digital frequency meter using complex programmable logic device FPGA, VHDL programming integration of all functional modules on a single chip. Functional modules, including time-base pulse generator, counters, and display data latch circuit 4. Design before the design of various functional modules, respectively, and debugging simulation results correctly, and then combine the various functional modules. Finally, for the overall simulation, download, be kind. As a result of the production of digital hardware design, stability, reliability is far higher than the use of single-chip microcomputer or analog means of the system, a simple peripheral circuits. The digital frequency meter to achieve the desired requirements of the variable-range measurement, measuring range 0.1Hz-9999MHz, accuracy up to 0.1Hz. Platform: |
Size: 412672 |
Author:严术骞 |
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Description: FIFO（先进先出队列）通常用于数据的缓存和用于容纳异步信号的频率或相位的差异。本FIFO的实现是利用
双口RAM 和读写地址产生模块来实现的.FIFO的接口信号包括异步的写时钟（wr_clk）和读时钟（rd_clk）、
与写时钟同步的写有效（wren）和写数据（wr_data） 、与读时钟同步的读有效（rden）和读数据（rd_data）
为了实现正确的读写和避免FIFO的上溢或下溢，给出与读时钟和写时钟分别同步的FIFO的空标志（empty）和
满标志（full）以禁止读写操作。-FIFO (FIFO queue) is usually used for data caching and asynchronous signal used to accommodate the frequency or phase differences. The realization of this FIFO is to use dual-port RAM and to read and write address generator module achieved. FIFO interface signals, including asynchronous write clock (wr_clk) and read clock (rd_clk), and write effectively write clock synchronization (wren) and write data (wr_data), clock synchronization and time effective reading (rden) and read data (rd_data) in order to realize the right to read and write and to avoid FIFO overflow or the underflow, is given with the time clock and write clock synchronization FIFO respectively empty signs (empty) and full logo (full) to prohibit the read and write operations. Platform: |
Size: 378880 |
Author:lsg |
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Description: VHDL语言的UART串行接口芯片程序,包括数据接收器、数据发送器和波特率发生器等。-VHDL language UART serial interface chip procedure, including data receiver, data transmitter and baud rate generator and so on. Platform: |
Size: 3072 |
Author:liukun |
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Description: CRC码产生器与校验器程序
Features ：
Executes in one clock cycle per data word
Any polynomial from 4 to 32 bits
Any data width from 1 to 256 bits
Any initialization value
Synchronous or asynchronous reset-CRC code generator and calibration program Features: Executes in one clock cycle per data word Any polynomial from 4 to 32 bits Any data width from 1 to 256 bits Any initialization value Synchronous or asynchronous reset Platform: |
Size: 5120 |
Author:Alex |
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Description: 现代电子系统课程设计
基于DDS技术利用VHDL设计并制作一个数字式移相信号发生器。
（1）基本要求：
a．频率范围：1Hz～4kHz，频率步进为1Hz，输出频率可预置。
b．A、B两路正弦信号输出，10位输出数据宽度
c．相位差范围为0～359°，步进为1.4°，相位差值可预置。
d．数字显示预置的频率（10进制）、相位差值。
（2）发挥部分
a．修改设计，增加幅度控制电路（如可以用一乘法器控制输出幅度）。
b．输出幅度峰峰值0.1～3.0V，步距0.1V，显示预置值。
-Modern electronic system design is based on DDS technology courses use VHDL to design and produce a digital shift Signal Generator. (1) the basic requirements: a. Frequency range: 1Hz ~ 4kHz, frequency step for the 1Hz, output frequency can be preset. b. A, B two sinusoidal signal output, 10-bit output data width c. Phase difference range of 0 ~ 359 °, stepping to 1.4 °, the phase difference value can be preset. d. Figures show that the frequency of Preferences (10 M), phase difference value. (2) to play a part of a. Modify the design to increase the rate of control circuit (for example, could use a multiplier to control the output rate). b. Peak-to-peak output rate of 0.1 ~ 3.0V, step 0.1V, show preset value. Platform: |
Size: 174080 |
Author:耳边 |
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Description: 基于ROM的正弦波发生器的设计：1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based design of the sine wave generator: 1. Sinusoidal waveform generator by the data storage module (ROM), waveform generator control module and latch module 2. Waveform data storage module (ROM) custom data width of 8 , address width of 6, can store 64 points sinusoidal waveform data, waveform data are obtained using MATLAB. 3. To 50MHz clock as input. Platform: |
Size: 98304 |
Author:宫逢源 |
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Description: 该波形发生器以单片机(MCS8031)为中心控制单元，由键盘输入模块、数码管显示模块、D/A波形发生模块dac0832、幅值调整模块组成。采用DDFS技术，先将要求的波形数据存储于EEPROM中，这样可以保证掉电以后波形数据不丢失。-The waveform generator to single-chip microcomputer (MCS8031) as the central control unit, by the keyboard input module, digital tube display module, D/A waveform occurred in module, the amplitude adjustment module. DDFS technology used, first the requirements of waveform data stored in EEPROM, so that after power-down waveform to ensure that data is not lost. Platform: |
Size: 172032 |
Author:litong |
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Description: 基于EPM7128的数字合成信号发生器（DDS）设计。通过对EPM7128编程，组合出地址累加器、数据锁存器、256*8位ROM空间。外接DA可实现正弦波输出功能-EPM7128-based signal generator for digital synthesis (DDS) design. EPM7128 through programming, the combination of address accumulator, data latches, 256* 8 ROM space. DA external sine wave output function can be realized Platform: |
Size: 354304 |
Author:xiaoyu |
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Description: 多功能波形发生器VHDL程序与仿真.实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成各种波形的线形叠加输出。
-Multi-function waveform generator and simulation of VHDL procedures. The realization of four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and magnitude of control output (square wave of duty cycle A is controllable), Arbitrary Waveform characteristics can store data and can reproduce the waveform, but also the completion of the linear superposition of a variety of output waveforms. Platform: |
Size: 10240 |
Author: |
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Description: 本文主要介绍的是采用直接数字频率合成的短波信号发生器，它主要以微电脑控制部分、直接数字频率合成（DDS）部分、数字锁相环频率合成部分、背光液晶显示部分、功率放大部分等组成。该软件系统采用菜单形式进行操作，操作方便明了，增加了很多功能。它通过启动DDS后，把内存缓存区的数据送到DDS后输出相应的频率，并把数据转换为BCD码，送到液晶显示器进行显示。该系统输出稳定度、精度极高，适用于当代的尖端的通信系统和精密的高精度仪器。-This paper describes the use of direct digital frequency synthesis of short-wave signal generator, which is part of a micro-computer control, Direct Digital Synthesis (DDS) of the digital part of PLL frequency synthesizer, backlit liquid crystal display of the power amplifier, etc. composition. The menu system uses the form of software to operate, easy to operate and clear, increase in the number of features. DDS through start after the memory cache after the data to the DDS output corresponding frequency, and the data is converted to BCD code to the LCD display. The output of the system stability, high precision for cutting-edge contemporary and sophisticated communication systems high-precision instruments Platform: |
Size: 466944 |
Author:xiang |
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Description: 实现4种常见波形正弦、三角、锯齿、方波（A、B）的频率、幅度可控输出（方波
--A的占空比也是可控的），可以存储任意波形特征数据并能重现该波形，还可完成
--各种波形的线形叠加输出。
-Achieve the four kinds of common sine wave, triangle, sawtooth, square wave (A, B) the frequency and amplitude controlled output (square wave- A duty cycle is controlled), can store arbitrary waveform feature data and can to reproduce the waveform, it can perform- all kinds of linear superposition of the output waveform. Platform: |
Size: 10240 |
Author:刘新 |
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Description: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA器件设计与实现UART。
-UART is a widely used serial data communication circuits. This design includes UART transmitter, receiver and baud rate generator. Design and Application of EDA technology, based on FPGA device design and implementation of UART. Platform: |
Size: 4096 |
Author: |
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Description: 基于ROM的正弦波发生器的设计
一．实验目的
1. 学习VHDL的综合设计应用
2. 学习基于ROM的正弦波发生器的设计
二．实验内容
设计基于ROM的正弦波发生器，对其编译，仿真。
具体要求：
1.正弦发生器由波形数据存储模块（ROM），波形发生器控制模块及锁存模块组成
2.波形数据存储模块（ROM）定制数据宽度为8，地址宽度为6，可存储 64点正弦波形数据，用MATLAB求出波形数据。
3.将50MHz作为输入时钟。
-ROM-based sine wave generator design
1. Purpose of the experiment
1. VHDL Integrated Design and Application of Learning
2. Learning ROM-based sine wave generator design
2. Experimental content
ROM-based sine wave generator design, its compilation, simulation.
Specific requirements:
1. Sine wave generator by the data storage module (ROM), waveform generator control module and latch modules
Two. Waveform data storage module (ROM) custom data width is 8, the address width of 6, can store 64-point sine wave data, wave data obtained using MATLAB.
3. The 50MHz input clock. Platform: |
Size: 17408 |
Author:爱好 |
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Description: UART是广泛使用的串行数据通讯电路。本设计包含UART发送器、接收器和波特率发生器。设计应用EDA技术，基于FPGA/CPLD器件设计与实现UART。-UART is a widely used serial data communication circuit. The design includes UART transmitter, receiver and baud rate generator. Application of EDA design technology based on FPGA/CPLD device design and implementation of UART. Platform: |
Size: 241664 |
Author:王志慧 |
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Description: 用VHDL语言编写的实现交织编码和解交织功能的代码。交织采用按行写入，按列读出的方法实现。主要包括：信源信号产生（20位的m序列），交织器，解交织器。为实现流水线的操作，采用了两个交织器和两个解交织器，当一个写入数据的时候，另一个读出数据。-Implementation using VHDL language features Interleaved Coded deinterleave code. Intertwined with by line write, read out by column method implementation. Include: source signal generator (20-bit m sequence), interleaver, interleaver solution. For the realization of the pipeline operation, using two solutions of the two interleaver and interleaver, when a write data, another read data. Platform: |
Size: 36864 |
Author:李修函 |
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Description: 时钟发生器用于生成不同的时钟信号clock、clk2、fetch与alu_clk，产生的时钟信号clk送往寄存器与状态控制器，时钟信号clk2送往数据控制器与状态控制器，信号fetch送往数据控制器与地址多路器，信号alu_clk送往算术逻辑单元。-Clock generator to generate different clock signals clock, clk2, fetch and alu_clk, generated clock signal sent to register with the state controller clk, the clock signal clk2 sent to the data controller and the state controller, the signal sent to fetch the data controller and address of the multiplexer, the signal sent to the arithmetic logic unit alu_clk. Platform: |
Size: 4096 |
Author:cccs |
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Description: 基于FPGA的DDS波形发生器--程序，如果需要产生输出不同的位数的波形，可以自行修改程序中的rom表中数据位数-FPGA-based waveform generator DDS- procedure, if the number of bits required to generate output of different waveforms in the program can modify data in the table the median rom Platform: |
Size: 1256448 |
Author:许聪 |
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